The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device having at least one memory cell which has a capacitor structure incorporating an improved electrode therein and a method for the manufacture thereof.
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been proposed a ferroelectric memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bithmuth tantalate (SBT) is used for capacitor in place of conventional silicon oxide film or silicon nitride film.
In FIG. 1, there is shown a cross sectional view setting forth a conventional semiconductor memory device 100 for use as FeRAM, disclosed in U.S. Pat. No. 5,864,153, entitled xe2x80x9cCAPACITOR STRUCTURE OF SEMICONDUCTOR MEMORY CELL AND FABRICATION PROCESS THEREOFxe2x80x9d. The semiconductor memory device 100 includes an active matrix 10 incorporating a metal oxide semiconductor (MOS) transistor therein, a capacitor structure 23 formed on top of the active matrix 10, a bit line 34, a metal interconnection 36 and a plate line 38.
In FIGS. 2A to 2E, there are illustrated manufacturing steps involved in manufacturing the conventional semiconductor memory device 100.
The process for manufacturing the conventional semiconductor memory device 100 begins with the preparation of an active matrix 10 having a silicon substrate 2, a MOS transistor formed thereon as a selective transistor, an isolation region 4 and a first insulating layer 16 formed on the MOS transistor and the isolation region 4. The first insulating layer 16, e.g., made of boron-phosphor-silicate glass (BPSG), is formed over the entire surface by using a chemical vapor deposition (CVD) technique. The MOS transistor includes a pair of diffusion regions 6 serving as a source and a drain, a gate oxide 8, a spacer 14 and a gate line 12.
In a subsequent step, there is formed on top of the active matrix 10 a buffer layer 18, a first metal layer 20, a dielectric layer 22 and a second metal layer 24, sequentially, as shown in FIG. 2A. The buffer layer 18 is made of titanium (Ti) and the first metal layer 20 is made of platinum (Pt). The dielectric layer 22 is made of a ferroelectric material. The buffer, the first and the second metal layers 18, 22, 24 are deposited with a sputter and the dielectric layer 20 is spin-on coated.
Thereafter, the second metal layer 24 and the dielectric layer 22 are patterned into a predetermined configuration. And then, the first metal layer 20 and the buffer layer 18 are patterned into a second predetermined configuration by using a photolithography method to thereby obtain a capacitor structure 23 having a buffer 18A, a bottom electrode 20A, a capacitor thin film 22A and a top electrode 24A, as shown in FIG. 2B. The buffer layer 18A is used for ensuring reliable adhesion between the bottom electrode 20A and the first insulating layer 16.
In a next step, a second insulating layer 26, e.g., made of silicon dioxide (SiO2), is formed on top of the active matrix 10 and the capacitor structure 23 by using a plasma CVD, as shown in FIG. 2C.
In an ensuing step, a first and a second openings 27, 28 are formed in the second and the first insulating layers 26, 16, thereby exposing the diffusion regions 6, respectively. A third and a fourth openings 30, 32 are formed on top of the capacitor structure 23 through the second insulating layer 26, thereby exposing portions of the bottom and the top electrodes 20A, 24A, respectively, as shown in FIG. 2D.
Finally, an interconnection layer is formed over the entire surface including the interiors of the openings 27, 28, 30, 32, and is patterned to form a bit line 34, a metal interconnection 36 and a plate line 38, thereby obtaining the semiconductor memory device 100, as shown in FIG. 2E.
Even though the aforementioned semiconductor memory device 100 and the method for the manufacture thereof is utilizing the buffer layer 18 to secure reliable adhesion between the bottom electrode 20A and the first insulating layer 16, it still suffers from a bad adhesion therebetween due to the different crystallographic properties from each other.
Furthermore, the bottom electrode 20A does not adhere to the second insulating layer 26 at the interface therebetween since the crystallographic property of the bottom electrode 20A is very different from that of the second insulating layer.
These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield.
It is, therefore, an object of the present invention to provide a semiconductor memory device having an improved adhesion between the bottom electrode and the insulating layers surrounding the bottom electrode.
It is another object of the present invention to provide a method for manufacturing a semiconductor memory device having an improved adhesion between the bottom electrode and the insulating layers surrounding the bottom electrode.
In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, including: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate, an isolation region for isolating the transistor and an insulating layer formed on top of the transistor and the isolation region, a bottom electrode formed on top of the insulating layer, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film, wherein the bottom electrode is divided into metal oxide portions and a metal portion sandwiched between the metal oxide portions.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method including the steps of: a) preparing an active matrix provided with a semiconductor substrate, a transistor including a pair of diffusion regions formed on top of the semiconductor substrate and a first insulating layer formed around the transistor; b) forming a first metal oxide layer on top of the first insulating layer; c) forming a first metal layer and a second metal oxide layer on top of the first metal oxide layer, subsequently; d) a dielectric layer on top of the second metal oxide layer; e) a second metal layer on top of the dielectric layer; and f) patterning the second metal layer, the dielectric layer, the second metal oxide layer, the first metal layer and the first metal oxide layer into a first predetermined configuration, thereby obtaining a capacitor structure.